Modern microprocessors may include one or more cores that are capable of performing operations typically associated with a traditional central processing unit (CPU).
Referring to FIG. 1, a multi-core microprocessor 100 is shown, which comprises one or more die 120 disposed in a mechanical package 110. Each die is comprised of one or more cores 130, one or more primary cache memory arrays 140, one or more secondary cache memory arrays 150, and additional circuitry and connectivity necessary for the proper operation of the microprocessor.
The cache memory arrays comprise a plurality of cache lines comprised of a plurality of bits that are used to store previously accessed instructions or data. Cache memory arrays are typically comprised of fast Static Random Access Memory (SRAM). Cache memory arrays are differentiated by their place in the hierarchical organization of memory within a system. For example, level one (L1) refers to small instruction and/or data cache memory arrays disposed on the microprocessor die and level two (L2) refers to larger instruction and/or data cache memory arrays also disposed on the microprocessor die, but further removed from the core than L1. It is well understood in the art that the hierarchical organization of memory and the use of cache memory arrays reduces main memory latency and improves system performance.
Single-core microprocessors typically have dedicated L1 and L2 instruction and data caches disposed on die. Multi-core microprocessors typically have a mix of dedicated and shared cache memory arrays. For example, Sun Microsystems' high end microprocessor is comprised of four core clusters, each comprised of four cores, resulting in sixteen total cores. Each core within a given core cluster shares L1 instruction and data caches and all core clusters share L2 instruction and data caches. One of ordinary skill in the art will recognize that there are a number of ways in which to organize cache memory arrays disposed in a microprocessor.
Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), and other semiconductor devices are also comprised of memory arrays utilized for a variety of purposes.
The fabrication of a semiconductor device comprised of a memory array is complicated by defects that are inherent in the fabrication process. There may be a number of defective memory cells within the memory array. Additionally, there may be a number of memory cells that fail to meet minimum electrical requirements and are deemed to be defective. These defects could be a single defective memory cell or multiple defective memory cells. Multiple defective memory cells may be present in a given row and/or column of the memory array. Multiple defective memory cells may span one or more rows and/or one or more columns of the memory array.
Accordingly, certain redundancy schemes have utilized banks of fuses to disable defective cells and enable redundant cells. In post fabrication processing, the defective cells are disabled and redundant cells are enabled through the use of a laser, banks of fuses, and related circuitry. Typically, two banks of fuses are required. A first bank of fuses is utilized to disable defective cells. Defective cells are disabled by triggering one or more fuses with a laser to create open circuits. A second bank of fuses is utilized to enable redundant cells. Redundant cells are enabled by triggering one or more fuses with a laser to create bridge circuits. Other prior art redundancy schemes have utilized shift registers.